An SET propagation EDA tool based on analytical glitch propagation model

Abstract

We present a complete EDA tool that quantifies the susceptibility of each node within a combinational circuit to SET propagation. The tool includes a fully analytical SET propagation model developed previously and considers both electrical and logic masking. After an initial path pruning phase based on logical analysis to determine true paths, the tool computes the minimum width and minimum height SET pulse propagating from each circuit node towards the circuit outputs. Internal nodes are ranked depending on its SET propagation susceptibility providing valuable information to the circuit designer about the weakest circuit nodes against ionizing radiation. Tool results are compared to exhaustive electrical-level simulations for a commercial 65nm CMOS technology and a 45nm open-cell technology showing excellent results.