Reducing scan-shift power through scan partitioning and test vector reordering

Abstract

Excessive test power dissipation results in over-testing, IR-drop, yield loss and even heat damage to the circuit under test (CUT). An efficient scan-shift power reduction scheme based on scan chain partitioning and test vector reordering is presented in this paper. After partitioning the scan chains into several segments equally, a heuristic ant colony optimization (ACO) algorithm is introduced to reorder the test vectors to minimize the clashes between the previous test response and current test vector, which leads to scan-shift power reduction further. Experimental results show that the proposal can achieve 3.48% scan-shift power reduction on average with the help of ACO test vectors reordering after scan partitioning. Furthermore, the proposed scan-shift power reduction technique can be acceptable for any scan-based testing architecture without affecting test application time, test fault coverage, performance and/or routing cost of the CUT.