Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures

Abstract

Dynamic power dissipation during scan-based testing of a CMOS digital circuit is reported to be a major issue of concern. The three main components of test power in scan based designs are the logic power, the sequential power and the clock power. This paper presents Integrated Scan cell and Test Vector reordering schemes for linear and non-linear (Double Tree) scan chains, with an objective to reduce the sequential test power. In this regard, it makes two important contributions: (a) It improves the scan cell reordering (SCR) algorithm proposed in Ref. [1] for the linear scan architecture. It then integrates this improved SCR algorithm with a Test Vector Reordering (TVR) strategy that results in further reduction of the sequential test power. (b) It proposes and evaluates scan cell and test vector reordering strategies for the double tree scan (DTS) architecture. It is also observed that for some classes of circuits the TVR provides more reduction of sequential test power than the SCR. Applying the proposed techniques on ISCAS benchmark circuits results in significant sequential test power reduction (with a maximum of 30% and 29.16% for linear and double tree scan architectures respectively) when compared to that output by a commercial tool.