Reduced comparators for low power flash ADC using TSMC018

Abstract

Flash converters have high speed conversion rate compared to other types of Analog to digital converter (ADC). As precision increases, Flash ADC requires large number of comparators compared to other ADCs. Hence, the increase in chip area, power consumption and cost of Flash converters makes trade off for many applications. So, the low power Flash ADC is aimed to be designed with less number of low power consumption comparators. The proposed Flash ADC of 4 bit resolution uses only four low power consumption comparators. The reference voltages from the diode connected transistorvoltage divider network is selected through the multiplexers and fed to the comparators. The proposed CMOS Flash ADC is implemented using Mentor Graphics EDA tool with MOS model library-TSMC 0.18um parameters.