Reduced bond graph modeling of semiconductor device thermal effects

Abstract

Faced with the problem of modeling complex and mixed-domain dynamic systems, system engineers use the bond graph formalism. Bond graph techniques are now used for modeling semiconductor devices in power electronics field. To have accurate models of power devices, it is necessary to take into account the thermal phenomena modeled by a thermal network. The thermal network describes the heat flow and the temperature evolution from the chip surface through the package and heat sink. To model these semiconductor devices, the bond graph model of the thermal and electrical parts must be described to illustrate how they are coupled, in order to build the device electrothermal model. In this paper, regardless of the switch state, the bond graph formalism application to power semiconductor devices, combining the electrical and thermal phenomena, is presented. A reduction procedure application to the semiconductor device thermal effects is also proposed in order to obtain a reduced electrothermal bond graph model.