Reconfigurable processor arrays with two-track switches

Abstract

To improve fabrication-time yield for processor arrays, spare processors and switching lattices are often incorporated, especially when each array contains a large number of processors. A routing algorithm for arrays with two horizontal routing tracks and two vertical routing tracks is proposed. Although the array has a smaller number of tracks than that used by other researchers, it is shown that the routing algorithm is able to explore the reconfigurability of the array, and the result is quite promising. Preliminary results show that two-track arrays can provide quite sufficient routing capability. >