Transitive closure and graph component labeling on realistic processor arrays based on reconfigurable mesh network

Abstract

A O(log/sup 2/ n) complexity parallel algorithm is presented for graph component labeling and transitive closure on reconfigurable processor arrays. Although lower complexity algorithms for the same tasks on reconfigurable processor arrays have been proposed, the reconfigurable processor arrays supporting such algorithms have communication capabilities which are neither scalable nor suitable for VLSI implementation. On the contrary the algorithm presented is designed for a realistic class of reconfigurable processor arrays, called polymorphic processor arrays, which is both scalable and suitable for VLSI implementation. >