Abstract
Today, the wireless communication is an emanating requirement of day to day process. Due to the noisy environment in wireless communication there is a need of coding system, which can provide high data rate with error free communication. The turbo codes also known as Parallel Convolutional Concatenated Code (PCCC) provides high data rate with bit error rate performance improvement in communication system. With the advent demand of miniaturization, an area efficient turbo decoder of constraint length 3 is proposed in this paper. The turbo decoder used a single SISO (Soft Input Soft Output) decoder architecture in this paper to reduce the area consumption. The SOVA (Soft Output Viterbi Algorithm) is used as a decoding algorithm in SISO decoders. It is based on two step algorithm. The proposed design is simulated using Matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. The performance of proposed Turbo decoder will be compared for FPGAs in terms of number of slice Flip-flops, LUTs and frequency. The Synthesis results show a 3% improvement in the utilized no. of slice flip-flop and 49% improvement in terms of frequency.
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