Performance analysis of Turbo decoder using Soft Output Viterbi Algorithm

Abstract

This paper presents the design and implementation of an efficient VLSI architecture for 3GPP-LET. Turbo decoder mainly consists of soft-input soft-output (SISO) decoders to achieve high throughput and interleaver and deinterleaver. Turbo decoder comprises of Branch Metric Unit(BMU), State Metric unit(SMU), Log-Likelihood Ratio Computation Unit(LLR), Add Compare Select Unit. Throughput of Turbo decoder depends on speed of ACS (Add Compare & Select) This paper, proposed a new ACS(Add Compare Select) unit consists of Carry-lookahed Adder, Digital Comparator & Multiplexer which increases the throughput & reduces the area of the design. In data transmission, turbo coding helps achieve near Shannon limit performance. Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are important blocks in today's communication systems to achieve the best possible data reception with the fewest possible errors. The proposed turbo decoder is based on the Soft Output Viterbi Algorithm (SOVA). For low bit error rate the Turbo Decoder Simulated using MATLAB. The entire architecture of Turbo decoder is coded using Verilog HDL and it is synthesized using Xilinx EDA with Spartan 3E.