Reconfigurable mesh-connected processor arrays using row-column bypassing and direct replacement

Abstract

This paper proposes an advanced reconfiguration scheme using row-column bypassing and direct replacement for two-dimensional mesh-connected processing-node arrays that makes an array usable for massively parallel computing and stand-alone computing in an efficient divided manner. This scheme uses an array providing a switching circuit in every node for row-column bypassing and a simple bypass network with a tree structure allocated to the array by graph-node coloring with a minimum inter-node distance of three for direct replacement. It can reconfigure a subarray with a regular matrix of free nodes usable for parallel computing in the array while allowing a small delay in the mesh connections but maintaining a communication path from every busy node being used as stand-alone computing to the outside of the array. The direct replacement is used for substitution of busy nodes which are not covered by row-column bypassing with free nodes located in the rows or columns to be bypassed, helping to enlarge the size of the reconfigured subarray. The bypass allocation with a minimum distance of three enables distributed communications and simple routing in the array while attaining a large success probability of the direct replacement. The proposed scheme is advantageous for constructing fault-tolerant massively parallel systems by using personal computers or workstations as processing nodes and Ethernet devices for interconnections.