Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder

Abstract

In this brief, we propose a reconfigurable hardware architecture of successive cancellation (SC) decoder with supporting multiple modes. We also develop three design techniques, including low-area quantization scheme (LA-QS), high-efficient frozen-bit control scheme (HE-FBCS), and grouping storage circuit (GSC). In the ASIC design implementation via TSMC 40-nm CMOS technology, it only has a core area occupation of 1.312 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and supports 4 operating modes, ranging from 1024 to 8192 bits. It operates at maximal operating frequency of 1.0 GHz, delivering a maximal throughput of 3.341 Gbps. As compared with state-of-the-art works, our innovative and reconfigurable multi-mode Polar decoder architecture owns superior chip performance, especially in terms of total chip area cost and system throughput.