Low-Complexity Successive Cancellation Decoder with Scan Chain

Abstract

This paper presents a low complexity implementation of Successive Cancellation (SC) decoder architecture for the polar codes with scan chain for fault testing. Here a modified p-node is proposed at the last stage of SC decoder to decode 2-bits in a single clock cycle. The proposed architecture is designed and implemented on Kintex Ultrascale+ FPGA, xcku5p-ffv9676. The proposed SC decoder displayed 63% reduction in latency compared to conventional SC decoder. Implementation results displayed a significant reduction in resource utilization as well as on-chip power compared to prevailing SC decoders.