Reconfigurable Concurrent Dual-Band Low Noise Amplifier with Dynamic Output Load Network for Software Defined Radio

Abstract

The design and detailed analysis of a Reconfigurable concurrent Dual-band LNA with Dynamic Output Load Network operating in 0.9GHz and 1.8GHz has been demonstrated in 0.18um CMOS process. A common source (CS) cascade topology with serial and parallel LC circuit based input matching was adopted. A new output load network made reconfigurable in terms of high gain(HG) and low gain(LG) mode through the output impedance seen at the respective nodes. The impedance nodes are controlled through control (CT H and CT L ) switches. Varactor tuning has been incorporated to input and output to optimize the circuit. The proposed LNA achieves a S 21 of 19 dB and 13 dB at 0.9 GHz and 1.8 GHz for high gain mode, and simultaneously 10 dB and 7 dB gain for low gain mode. The extracted simulations shows with noise figure (NF) of 4 dB and 4.2 dB at high gain mode and 3.3 dB and 4 dB at low gain mode respectively.