Abstract
In this paper we reconfigure the input boundary-scan register to an operable test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal. The output boundary-scan register is reconfigurable to operate as an output response analyser that is driven by the logic circuit for the predetermined number of clock cycles upon receipt of the built-in self-test control signal. A family of input and output boundary-scan cells that can be reconfigured as a linear feedback shift register and as a multiple-input shift register is disclosed.
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