Recessed Channel Ferroelectric-Gate Field-Effect Transistor Memory With Ferroelectric Layer Between Dual Metal Gates

Abstract

In this study, we demonstrate a novel recessed channel ferroelectric field-effect transistor (FeFET) with gate metal/ferroelectric (FE) layer/inter-metal (IM)/interlayer (IL)/Si stacks, which can be called as dual metal gates recessed channel FeFET (DM-RFeFET), for nonvolatile memory applications with high performance and robust reliability. Through technology computer-aided design (TCAD) simulations with calibrated FE and device model parameters, it is revealed that the DM-RFeFET can have the wide memory window (MW) and the possibility of endurance improvement by maximizing the area ratio of FE and IL without sacrificing the footprint. Furthermore, the guidelines for the DM-RFeFET design are provided in terms of recess depth and additional high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> blocking layer between IM and IL to maximize the MW and to minimize IM charging by the gate leakage current.