Recent Developments in Panel Level Packaging

Abstract

Panel Level packaging (PLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration also larger substrates formats are targeted. Fan-out Wafer Level manufacturing is currently done on wafer level up to 12/300 mm and 330 mm diameter respectively. For higher productivity and therewith lower costs, larger form factors are introduced. Instead of following the wafer level= roadmaps to 450 mm, panel level packaging might be the next big step. Upscaling of technology when moving from wafer to panel level as well as the use or adaptation of existing large area tools and materials as e.g. from Printed Circuit Board (PCB) or Liquid Crystal Display (LCD) manufacturing is not possible. Additionally, the missing standardization in sizes is another challenge. Considered panel dimensions ranges from 300x300 mm $^{2}$ to 457x610 mm $^{3}$ or 510x515 mm $^{2}$ up to 600x600 mm $^{2}$ or even larger. The paper will describe recent developments along the process chain including materials for carrier selection, encapsulation and redistribution layer as well as the related process and equipment options. Especially the redistribution layer (RDL) application offers a variety of technology options. In addition, main challenges as warpage, die shift and panel handling in PLP will be discussed. However, for industrialization also the understanding of the cost structure and cost opportunities are important – also referring to the different technology options. Therefore, a highly granular cost model is introduced and application scenarios are presented.