Abstract
This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating-gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride-based SONOS devices as well as nanocrystal (NC)-based devices. For SONOS devices, results are presented for optimization of the nitride layer to obtain the best characteristics, and the simulation of the program/erase transients. For NC devices, experimental characteristics of single and dual layer cells, as well as simulation results are presented.
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