Abstract
Energy efficiency is a key design consideration in wireless systems. Energy efficient system design requires systematic optimization at all levels of the design abstraction ranging from process technology and logic design to architectures, algorithms and networking. The energy expended per operation continues to improve as the power supply voltages are scaled. Sub-threshold circuit design provides a major opportunity to dramatically reduce the power dissipation of digital integrated circuits. The opportunities and challenges associated with sub-threshold design will be presented. Idle-mode power (i.e., leakage) must also be carefully managed in sub-90nm CMOS and will require the use of techniques such as fine-grain power gating and ultra-dynamic voltage scaling. 3-D integration also presents an interesting opportunity for power savings — the potential power savings of this technology will be presented for a 3-D FPGA circuit. Specific examples of power management in integrated circuits will be presented, focusing on wireless sensor networks and impulse based ultra-wideband communications as drivers.
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