Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization

Abstract

With the rapid growth in the use of portable electronic devices, more emphasis has recently been placed on low-energy circuit design. Digital subthreshold and nearthreshold CMOS circuit designs offer significant energy savings by operating at a reduced power supply voltage. However, these energy savings come at a critical cost to performance, restricting their use to severely energy-constrained applications. This paper presents a hybrid methodology that integrates characterized nearthreshold and subthreshold standard cells into high-performance functional modules. Within these functional modules, energy minimization is achieved while satisfying performance constraints by replacing non-critical path logic with nearthreshold and subthreshold logic cells. Specifically, the critical path method is used to bind the timing and energy constraints of the design. The design methodology was verified and tested with several benchmarks, including a cryptographic hash function, Skein. An average energy savings of 41.15% was observed at a circuit performance degradation factor of 10. The energy overhead of the level shifters accounted for at least 8.5% of the optimized circuit energy, with an average energy overhead of 26.76%. A heuristic approach for estimating the energy savings of the optimized design is also presented.