Abstract
This paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.
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