Real-time morphological pipeline architecture using high-capacity programmable logical devices

Abstract

Mathematical morphology is a very important image analysis area that uses set theory tools to study shapes. The basic operations in mathematical morphology are dilation and erosion, and these can be used to construct more complex operations. Low-level image processing often uses dedicated computing hardware for repetitive processing over large data structures. High-capacity programmable logic devices (HCPLDs) have increasingly been used for the fast development of real-time image processing systems. In this paper we present a pipeline architecture, using high-capacity programmable logic devices, for real-time mathematical morphology operations. The developed architecture can process (512×512) pixel binary images and has flexible stages that can be reprogrammed according to the shape and size of the structuring elements used in the morphological operations. Tests performed over the architecture demonstrated that it performs well when compared to similar architectures and that it is an efficient choice for dedicated morphological image processing operations.