Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA

Abstract

In recent years, the real time hardware implementation of LMS based adaptive noise cancellation on FPGA is becoming popular. There are several works reported in this area in the literature. However, NLMS based implementation of adaptive noise cancellation on FPGA using Xilinx System Generator (XSG) is not reported. This paper explores the various forms of parallel architecture based on NLMS algorithm and its hardware implementation on FPGA using XSG for noise minimization from speech signals. In total, the direct form, binary tree direct form and transposed form of parallel architecture of normalized least mean square (NLMS), delayed normalized least mean square and retimed delayed normalized least mean square algorithms are implemented on FPGA using hardware co-simulation model. The performance parameters (SNR and MSE) of these algorithms are analyzed for the adaptive noise cancellation system and the comparison is made with parallel architectures of least mean square (LMS), delayed least mean square, and retimed delayed least mean square algorithms respectively. The hardware utilization of all the said algorithms are also analyzed and compared. The result shows that NLMS based implementations outperform than that of LMS for all forms of parallel architecture for the given parameters with negligence increase in device utility. The binary tree direct form of retimed delayed NLMS achieves the maximum SNR improvement (39.83 dB) in comparison to other NLMS variants at the cost of optimum resource utilization.