Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM

Abstract

The ideal goal of semiconductor quality assurance is to provide zero defective parts to the customer. In practice this goal is limited by test quality and test cost due to expensive ATE resources. It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high costs of testing involved. Comprehensive functional tests to find all detectable faults typically have large test times resulting in a prohibitive cost. Work has been done in the field of digital testing with patterns where statistical tools are used in order to optimize the test cost and DPPM by real-time analysis. Our goal is to propose an Analog to Digital Converter (ADC) Built in Self Test (BiST) scheme which has compatibility with similar dynamic optimization measures. Multiple variants of Very Low Cost (VLC)- ATE have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hard-ware cost. Systems containing mixed-signal/RF components typically can not be tested on such ATE due to limitations/lack of analog/RF stimulus and measurement modules on VLC-ATE. This paper proposes a hybrid BIST scheme for ADCs to enable full production-quality testing as well as reduced coverage testing with VLC-ATE. We cover on-chip stimulus generation for a fully functional at-speed test as well as for a low-cost-reduced-coverage approach. Results for the BIST scheme are presented along with a discussion on implementation feasibility and merits. A vector based approach for observing ADC outputs is discussed which could be used with this scheme on VLC-ATE.