Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems

Abstract

This paper describes an optimization technique for finding test solutions for embedded core-based systems. For embedded systems the traditional external tester based test is often unfeasible and therefore different self-test solutions are sought after. Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems. The results will be illustrated with several experimental results.