Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Sneh Saurabh,Shelly Garg

doi:10.1109/jeds.2020.3025266

Abstract

Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this article, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFF-state current (I ON /I OFF ) ratio of order ~10 9 . Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

Highlights

Tunnel field-effect transistors (TFETs) are being actively investigated for futuristic energy-efficient applications due to their excellent subthreshold swing [1]–[6]
REALIZING XNOR FUNCTION USING TFET-XNOR STRUCTURE In [9], the gate–source overlap is shown to inhibit the band-to-band tunneling (BTBT) near the surface of a double-gate TFET (DGTFET) when the inputs are dissimilar, reducing the IOFF in the device
The DGTFET implementing XOR function turns on when the input is either “01” or “10”, the output node is pulled to Gnd

Summary

INTRODUCTION

Tunnel field-effect transistors (TFETs) are being actively investigated for futuristic energy-efficient applications due to their excellent subthreshold swing [1]–[6]. REALIZING XNOR FUNCTION USING TFET-XNOR STRUCTURE In [9], the gate–source overlap is shown to inhibit the BTBT near the surface (near the top gate, along cutline XX , and near the bottom gate, along cutline ZZ ) of a DGTFET when the inputs are dissimilar, reducing the IOFF in the device. This is in contrast to the AND function realization in [9], where only gate–source overlap is used.

IMPLEMENTATION OF XNOR AND XOR GATES

CONCLUSION