Realizable Reduction of Multi-Port RCL Networks by Block Elimination

Abstract

In this paper a block circuit elimination method is proposed for realizable reduction of resistor-capacitor-inductor (RCL) networks. It is an extension of a recently published realizable RC reduction method, called HD-TICER (high-dimensional time-constant equilibration reduction), to reduction of multi-port RCL networks. A modified nodal analysis (MNA) formulation is adopted in a setting for dealing with the inductive elements, which is suited for developing a realizable high-dimensional reduction scheme. A new matrix-based method is presented to establish the basic computation scheme, which seems more intuitive than the previously employed driving point impedance (DPI) method. Furthermore, a pole-zero based low-order moment matching method is introduced for the purpose of circuit recovery after reduction. The main advantages of the proposed reduction method include: 1) an intuition-based topological formulation and reduction computation method, 2) a natural port preserving reduction method, and 3) an easy-to-implement circuit recovery procedure. Experimental numerical implementation has validated the effectiveness of the proposed reduction method. Comparison to other existing methods further highlights multiple benefits of this new circuit reduction method.