Abstract
We have designed, fabricated and successfully tested digital error-correction circuits to improve the performance of superconductive flash analog-to-digital converters (ADCs). The comparators coding the most significant bits (MSBs) are the least sensitive to the input signal, and therefore have the most threshold errors due to jitter and threshold misplacement. These errors are completely eliminated by implementing an ADC architecture using two comparators per bit, and employing logic to encode bit N by looking back to the state of the (N-1) bit. In this way, all code transitions are derived from the least significant bit (LSB) comparators. The MSB comparators are used only to encode the LSB data.
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