Abstract
Carry Select Adder (CSLA) is used for arithmetic operations for better speed at the expense of area and power. In this paper we present novel structure of Conditional Binary to Excess-1 adder based on carry select adder design on gate level. Regular CSLA is area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and a Binary to excess-1 circuit instead of using dual RCA. A conditional BEC block is proposed which can be implemented in place of regular BEC block and multiplexer to add one to the output of modified RCA or pass the output without any change. This approach reduces necessity of multiplexers for CSLA hence reduce delay, area and power consumption compared to BECCSLA. Characteristics of modified RCA are compared with regular CSLA and two recent CSLA designs with SQRT structure. Result and analysis shows modified CBEC-CSLA have better area and power consumption than the regular dual RCA-CSLA, CBEC-MRCA, BEC based carry select adder and CS- based CSLA.
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