Abstract

Digital infrared (IR) focal plan array (IRFPA) is one of the most significant characteristic of advanced IR imaging systems, it is implemented by integrating ADCs into the readout integrated circuit (ROIC). Successive Approximation Register (SAR) ADC is popular for column-level ADC architecture since it has low power and high resolution. In this paper a 14-bit RC hybrid SAR ADC with unary capacitor array is proposed, it has better linearity performance area compared with conventional SAR ADC. The proposed SAR ADC introduces resistor ladder for the last 6-bit conversion and it is shared by the whole SAR ADC array, so single SAR ADC’s layout’s length can be reduced, The proposed SAR ADC is designed in 130 nm standard CMOS process, the size of the SAR ADC core is 30 μm × 560 μm. the post simulation result show that its power consumption is 102 μW when the sampling rate is 100 kHz, and the worst DNL is 0.4 LSB when mismatching of 0.2% of capacitor array is introduced. The proposed SAR ADC suits for digital IRFPA applications.

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