Abstract
Fault Injection (FI) is the most popular technique used in the evaluation of fault effects and the dependability of a design. Fault Simulation/Emulation (S/E) is involved in several applications such as test data generation, test set evaluation, circuit testability, fault detection & diagnosis, and many others. These applications require a faulty module of the original design for fault injection testing. Currently, Hardware Description Languages (HDL) are involved in improving methodologies related to the digital system testing for Field Programmable Gate Array (FPGA). Designers can perform advanced testing and fault S/E methods directly on HDL. To modify the HDL design, it is very cumbersome and time-consuming task. Therefore, a fault injection tool (RASP-FIT) is developed and presented, which consists of code-modifier, fault injection control unit and result analyser. However, in this paper, code modification techniques of RASP-FIT are explained for the Verilog code at different abstraction levels. By code-modification, it means that a faulty module of the original design is generated which includes different permanent and transient faults at every possible location. The RASP-FIT tool is an automatic and fast tool which does not require much user intervention. To validate these claims, various faulty modules for different benchmark designs are generated and presented.
Highlights
Hardware Description Languages (HDL) have been involved in improving various methodologies related to digital system testing during the last few decades
The RASP-FIT tool is fast and user-friendly and it takes an appropriate time for the generation of faulty modules of the original design
Authors studied the recently developed fault injection tools based on instrumentation technique in the Field Programmable Gate Array (FPGA) development flow, such as, tools that work on the net-list developed after the synthesis process [14], [15], [16], some tools based on the instrumentation technique on the code level [18], [17], and using some hybrid techniques [19], [20], [21], [22]
Summary
Hardware Description Languages (HDL) have been involved in improving various methodologies related to digital system testing during the last few decades. Based techniques are involved in testing, dependability analysis and fault simulation/emulation applications [5]. Designs implemented on the FPGA are prone to errors and failures, due to radiations and several other reasons, so it is necessary to test and verify the designs Both testing and verification involve a deliberate introduction of faults in the System Under Test (SUT). There are several reasons for involving FPGA in developing of fault injection techniques and tools, such as prototype availability of designs (for simulation), fast emulation ( the high speed of injections), more on-chip area availability and www.ijacsa.thesai.org
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