Radical low-slung influence 12-Bit SAR ADC

Abstract

Listen

Translate article

This paper presents a 12-bit SA-ADC for portable low power wireless sensor systems. The proposed SA-ADC operates for rail-to-rail input range and achieves low power consumption. Split capacitor array-based DAC and a novel charge-integration based dynamic comparator are used for low power consumption of the ADC. Measured DNL and INL are −0.59/0.67 LSB and −1.2/1.33 LSB respectively. At sampling rate of 100-kS/s with 1.8-V supply, the ADC consumes only 2-Μw power and achieves a SNDR of 64.42-dB, SFDR of 71.2-dB resulting in an FoM of 14-fJ/Conversion-step. The ADC core occupies an area of 0.238-mm2 and is fabricated in AMS 0.35-μm CMOS technology.