Abstract
In this paper we propose radiation-hardened flip-flops (FFs) with small area and short delay overheads in a 65 nm fully depleted silicon on insulator (FDSOI) process. We designed two FFs composed of a guard-gate to eliminate SET pulses in the latch. Although the number of additional transistors is only two, one of the proposed FFs has high soft error tolerance at CLK =1. Although the number of additional transistors is six, the other has high soft error tolerance at CLK =0 and 1. We evaluated the radiation hardness of the newly designed structure by device simulations. Simulation results show that the stored values of the proposed FFs are not upset even though a charged particle with LET of 60 MeV-cm2/mghits.
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