Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder

Abstract

A multiple node upset tolerant, 1.6 Gb/s (8158, 7136) and (4088, 3360) low-density parity-check encoder was implemented in a five-metal, 0.25 mum CMOS process. Temporal separation coupled with single-event radiation tolerant flip-flops was used to harden the data path. A reduced sensitive cross-section combinational logic structure was used to harden the custom multiply accumulate blocks. This circuit structure is composed of a dual-rail NMOS-only pass-transistor network driving a cross coupled output buffer. By adding the output buffer section, only a small region of the buffer itself is vulnerable for propagation of a single-event transient. Single-event upset immunity with a linear energy transfer threshold of greater than 33 MeVldrcm2/mg and a saturation cross-section of just 0.075 mum2/bit was achieved for the 4 K encoder. A linear energy transfer threshold of greater than 17 MeVldrcm2/mg with a saturation cross-section of just 0.3 mu m2/bit was achieved for the 8 K encoder. This results in a CREME96 expected mean time between failure of 1700 years for a geosynchronous orbit. Multiple node upsets as a problem increases as smaller geometry processes are used for space electronics. A mathematical basis for this reduced cross-section, multiple upset combinational logic design method is presented.