Abstract
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead.
Highlights
Semiconductor devices are becoming susceptible to particle strikes as they shrink to the nano-scale.There are two major negative effects caused by particle strikes: single event upset (SEU) [1] and single event latchup (SEL) [2].When radiation-induced particles with sufficient energy hit the silicon substrate of a CMOS chip, a large number of electron-hole pairs are generated and an undesired short-duration current may be formed, which can change the output of a logic gate
This paper proposes an architecture that allows NULL Convention Logic (NCL) circuits to recover from a Single Event Upset (SEU) or Single Event Latchup (SEL) fault without any data loss
THmn gates have n inputs; at least m of the n inputs must be asserted before the output will become asserted; and NCL threshold gates are designed with hysteresis state-holding capability, such that all asserted inputs must be de-asserted before the output will be de-asserted
Summary
When radiation-induced particles with sufficient energy hit the silicon substrate of a CMOS chip, a large number of electron-hole pairs are generated and an undesired short-duration current may be formed, which can change the output of a logic gate. This is called a soft error or single event upset (SEU). A spurious current spike induced by an ionizing particle in one of these transistors may be amplified by the large positive feedback of the thyristor This will cause a virtual short between power and ground, resulting in a single-event latchup (SEL). THmn gates have n inputs; at least m of the n inputs must be asserted before the output will become asserted; and NCL threshold gates are designed with hysteresis state-holding capability, such that all asserted inputs must be de-asserted before the output will be de-asserted
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