Radiation hardened high resolution timing generator

Abstract

A high resolution timing generator is used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented using digital Delay-Locked Loop (DLL). As DLLs are vulnerable to single event effects, the propagation of single-event transients (SETs) single event transients (SETs) is a significant reliability challenge for DLL. The errors signatures following an ion strike in Voltage-Controlled Delay Line (VCDL) can be mitigated using the dual controlled differential delay circuit in combination with sensitive node active charge cancellation (SNACC) for biasing circuit of VCDL. The dual controlled differential delay circuit based VCDL has faster locking with reduced duty cycle error.