Radiation Hardened Design of Pipeline and Register File in Processor

Abstract

With the development of aerospace technology and integrated circuit (IC) technology, the processor, as the core component of the spacecraft electronic device, is highly susceptible to the space high-energy particle radiation that can generate single event upset (SEU), Therefore, it is of great significance for the research of processor radiation hardened design. Considering the processor's speed, area and power overhead and the final hardened performance, based on the OR1200 processor platform, this paper proposes a technique to protect most signals by using the interleaved parity codes combined with the pipeline restart and partial signals by using the Triple Modular Redundancy (TMR) for the pipeline in processor. As multiple bits upsets (MBU) have become an serious issue for memory reliability, this paper also protects the register file in processer by using error correction codes with four adjacent errors correction and refreshing the register file with an exception trigger. Finally, both proposed techniques are verified and evaluated effectively. The result indicates that the SEU in pipeline and the MBU in register file can be effectively mitigated.