Abstract
Level shifting radiation hardening by design input and output (I/O) pads on a 90 nm process using triple modular redundancy for single event effect (SEE) mitigation with high total ionizing dose (TID) immunity are described. The designs use annular NMOS transistors for both thin and thick gate transistors. SEE mitigation is experimentally demonstrated by heavy ion measurements with LET <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> up to 220 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg with no failures. Measurements of the I/O standby leakage current after TID irradiation to 2 Mrad(Si) show no standby current increase.
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