Abstract

In this paper, a radiation-hardened by polar design 14T (RHPD-14T) SRAM cell for space applications is proposed. Performance of the proposed RHPD-14T cell is analyzed by estimating various design metrices with 65-nm complementary metal-oxide-semiconductor (CMOS) technology. The proposed RHPD-14T can tolerate all single-node upset and partial double-node upset based on combining radiation hardened by polar design technology together with reasonable layout topology. Simulation results show that write access time of RHPD-14T is 1.83×/1.59×/1.56×/1.12×/1.05× shorter than RSP-14T/QUCCE-10T/DICE/S4P8N/We-Quatro(@VDD=1.2V). Word line write trip voltage of RHPD-14T is 2.67×/2.22×/1.35×/1.29×/1.26× higher than QUCCE-10T/DICE/We-Quatro/S4P8N/RSP-14T (@VDD=1.2V). Hold static noise margin of RHPD-14T is 14.85×/7.15×/1.05× higher than DICE/S4P8N/RHPD-12T (@VDD=1.2 V). In addition, Monte Carlo (MC) simulations have proved that RHPD-14T has low fluctuation, strong stability, stable recovery ability and strong single effect upset (SEU) hardened.

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