Quick Median Filtering Algorithms Based on FPGA

Abstract

Median filtering is an important approach in digital image processing for noise elimination. An improved median filtering algorithm (IMFA) is proposed which can be implemented with only 17 comparisons and 6 clocks delay for 3×3 median filtering mathematical model based on field programmable gate array (FPGA). The algorithm benefits from the parallel processing and pipelining structure of FPGA hardware. At first, the characteristics, basic operational principle and computing process of the IMFA are presented. And then the algorithm using modular technique and top-down design flow methodology with Verilog HDL are programed. At last, some simulation verifications for the algorithm by ModelSim and experimental verification on FPGA hardware platform are carried out. The IMFA can get a large number of data throughput and more quickly processing speed and less hardware resources than similar filtering algorithms.