Quick and exhaustive descrambling methodology for high-density static random access memories using voltage contrast

Abstract

The external test previous to any failure analysis of a static RAM provides the logical address of each failure. We developed a methodology allowing a fast mapping of SRAMs, passivated or not, by voltage contrast in a scanning electron microscope, with minimum initial information. It uses voltage coding and the phase-selective voltage contrast. The first observations permit to distinguish the row bits from the column bits, and to sort the address bits according to the order of geometrical binary weight. The second part of the mapping consists in determining the symmetries associated with each address bit. Voltage coding observation needs only a few images. The second method requires at least as many images as address bits, but can be efficiently used with buried lines. This methodology was designed to be efficient whatever the matrix map may be. It was applied successfully on 64 kbit to 1 Mbit passivated CMOS SRAMs.