Quantitative analysis and prediction of experimental observations on quasi-static hysteretic metal–ferroelectric–metal–insulator–semiconductor FET and its dynamic behaviour based on Landau theory

Abstract

Due to internal voltage amplification induced by the negative capacitance of ferroelectrics, the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) FET has been widely investigated to explore its potential application in low power devices. Based on Landau theory and stability criterion, a simulation program is implemented and MFMIS structure is quantitatively analyzed. The results show that it can be appropriately designed for both integrated circuits and memory devices by tuning capacitances contributed by MOSFET dielectric stack and ferroelectrics. Our simulation results on electrical characteristics of ferroelectric devices agree well with both quasi-static and dynamic experimental observations. The influence of the ferroelectric/dielectric layer thickness and area as well as temperature on hysteretic polarization-electric field characteristic of a ferroelectric are successfully explained. For a C–V loop sweeping over the gate voltage in MFMIS, possible asymmetry in the accessible negative capacitance region is also interpreted. Moreover, experimentally observed reduction in the equivalent capacitance of the ferroelectric–dielectric bilayer at high frequency is confirmed by Landau–Khalatnikov theory based simulation. Our work provides a more complete and explicit analytical treatment to understand the effect of negative capacitance of a ferroelectric on device performance.