Quantifying the impact of uncertainty in embedded systems mapping for NoC based architectures

Abstract

We describe a modeling framework to capture and account for uncertainty in design parameters in embedded systems. We then develop an uncertainty-aware solution to the problem of mapping in embedded systems that uses Network-on-Chip (NoC) based architecture platforms. The problem of mapping is formulated as a multi-objective - reliability, performance, and energy consumption - optimization problem. To solve this problem, we propose a solution based on the NSGA-II genetic algorithm and Monte Carlo simulation techniques. The solution is implemented as a computer-aid design tool that can generate robust 3D Pareto frontiers in the solution space formed by the design objectives of reliability, performance, and energy consumption. Comparison to several state-of-the-art models and solutions for the mapping problem, indicate that significant differences in the actual values of the design attribute of interest exist when one considers uncertainty in design parameters. For example, in the case of mapping with reliability as the only objective, 10% uncertainty in design parameters can lead to a 10.06% difference in MTTF estimation. In the case of mapping with execution time and energy consumption as objectives, the difference in 2D Pareto frontiers due to 10% uncertainty in design parameters can be up to 7.9%. These differences are important because they can mislead the overall optimization process of mapping toward suboptimal solution points. The DESUU-NOC tool that implements the proposed multi-objective mapping algorithm has as a main feature and contribution of this paper the ability to generate 3D Pareto frontiers comprised of robust solution points.