Quantification of Shallow-junction Dopant Loss during CMOS Process

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We analyzed dopant concentration and profiles in source drain extension (SDE) by using in‐line low energy electron induced x‐ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet‐resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet‐etching removal during photo resist cleaning, 2) out‐diffusion, and 3) deactivation by post‐thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet‐etching removal and out‐diffusion are the most significant causes for dopant loss in n‐SDE and p‐SDE, respectively.