Abstract
In the last decade we have seen a shift towards a broader application of information on IC manufacturing defects. Here an overview is given of the methods used to gather data on the defects with a focus on local defects in the interconnection layers. Next this information is applied to determine a model describing the geometrical aspects of such defects. This model is used to arrive at a definition of hard faults and soft faults and to derive a relationship between the relative number of occurrence for either fault. Because the electrical impact of some of the soft faults will be closely related to the behavior of small open circuits or gate-oxide shorts, this relationship is an indication for the extent of the quality and reliability problems. >
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