Abstract
Binary adders are one of the most recurrent architectures in digital VLSI design, and the choice of adder architecture can boost or bust the overall performance of the design. Parallel-Prefix Adders are preferred over conventional adders for higher wordlengths. In this paper, a comprehensive, qualitative and quantitative analysis of popular Parallel-Prefix Adders for various wordlengths (N = 4, 8, 16 and 32) is presented. The adders are implemented using VHDL coding and Vivado 2016.2 HLx platform targeted for Basys3 board and compared on the basis of Device Utilization, Speed and Power Consumption. Results indicate that Kogge–Stone adder is the fastest adder with $$F_{max}$$ = 104.93 MHz but is most area-power inefficient consuming 133 LUTs and 23.756 W power at 10 GHz. Sklansky adder is most power efficient consuming 22.857 W power at 10 GHz. Brent–Kung adder is area optimum consuming 62 LUTs.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
