Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits

Abstract

For optimal operation, the Clock and Data Recovery (CDR) circuit requires perfect quadrature between In-phase and Quadrature phase clocks. These clocks are used to sample the Data and the Edge information so as to enable the CDR to align the Receiver clock to the centre of Data eye. Any error in quadrature between the two clocks results in higher CDR jitter. Quadrature error mainly comes from the clock-path mismatch and also from mismatch between the In-phase and Quadrature-phase interpolators. A novel Quadrature Error Compensation (Calibration) mechanism to overcome the quadrature error is implemented and discussed in this paper. An improvement of 30% in the CDR jitter was obtained with the proposed mechanism for a 5 Gbps (PCIe Gen2) link implemented in a 45nm process.