High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

Abstract

A Semi-Digital Clock and Data Recovery (CDR) circuit implemented in 45 nm SOI process is discussed. The CDR uses two analog phase interpolators to generate in-phase and quadrature-phase clocks to sample incoming data. Due to onchip process variations, the phase interpolators exhibit a nonlinear behavior. More so, this behavior is not similar in the two phase interpolators, i.e. there is a mismatch between them. This mismatch gives rise to quadrature error between the two clocks. The impact of this quadrature error on CDR jitter is highlighted for a data rate of 5.0 Gbps (PCIe Gen2 protocol). We propose a novel mechanism to mitigate the effect of this mismatch between the phase interpolators by tracking out the quadrature error. The scheme improves CDR jitter by 29%.