Abstract
Die-stacking technology is expanding the space diversity of on-chip communications by leveraging through-silicon-via (TSV) integration and wafer bonding. The 3D network-on-chip (NoC), a combination of die-stacking technology and systematic on-chip communication infrastructure, suffers from increased thermal density and unbalanced heat dissipation across multi-stacked layers, significantly affecting chip performance and reliability. Recent studies have focused on runtime thermal management (RTM) techniques for improving the heat distribution balance, but performance degradations, owing to RTM mechanisms and unbalanced inter-layer traffic distributions, remain unresolved. In this study, we present a Q-function-based traffic- and thermal-aware adaptive routing algorithm, utilizing a reinforcement machine learning technique that gradually incorporates updated information into an RTM-based 3D NoC routing path. The proposed algorithm initially collects deadlock-free directions, based on the RTM and topology information. Subsequently, Q-learning-based decision making (through the learning of regional traffic information) is deployed for performance improvement with more balanced inter-layer traffic. The simulation results show that the proposed routing algorithm can improve throughput by 14.0%–28.2%, with a 24.9% more balanced inter-layer traffic load and a 30.6% more distributed inter-layer thermal dissipation on average, compared with those obtained in previous studies of a 3D NoC with an 8 × 8 × 4 mesh topology.
Highlights
Since the mid-2000s, a chip multiprocessor (CMP) has been widely used to overcome the limitations concerning instruction-level parallelism and power walls in a single-thread/core processor [1]
Excessive excessive blocking blocking occurs occurs as the as the number number of throttling of throttling nodes nodes increases, increases, resulting resulting in ain negative a negative performance, performance, owing owing to reduced to reduced routing routing algorithms route packets with information predicted at a specific time and it is challenging to flexibility
The contribution of this study is the proposal of a Q-function-based traffic- and thermal-aware adaptive routing (QTTAR)
Summary
Since the mid-2000s, a chip multiprocessor (CMP) has been widely used to overcome the limitations concerning instruction-level parallelism and power walls in a single-thread/core processor [1]. The processor nodes in the top layer farthest from the heat sink encounter efficiency [8], as shown in. The TSVs used in stacked structures are constrained by larger bonding areas, microfluidic processes that are widely used in other applications, such as fluid networks or chips [10]. In microfluidic processes that are widely used in other applications, such as fluid networks complicated scaling processes with smaller feature sizes and sharp decreases in the yield as the the TSVs usedthe in[11,12], stacked constrained byconstrained larger areas, complicated or chips of TSVs used in stacked structures by larger bonding areas, number. Is classified intoto proactive pre-operation approaches and[9,15,16]
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