Abstract
This paper investigates the underlying physics of a SRAM device utilizing three-state Quantum Dot Gate (QDG) FETs by building up the physics from the general QDG-FET, its relation to the QDG-Inverter, and ultimately, the QDG-SRAM. The resulting equations from the exploration of the device physics were utilized to create a simulation within SIMULINK. From the simulation, it was found that in addition to being able to store the “1” and “0” states that are customary for an SRAM device, there is also the ability to store an intermediate state and a pseudo-state as a result of the intermediate state, allowing for the possibility of a 2-bit SRAM device in the same spatial constraints of a conventional SRAM unit cell. Additionally, the experimental results of the QDG-SRAM half-cell and the implications of utilizing a 4 state device to create either a 4 state SRAM cell or a 6 state SRAM cell with two pseudo-states are also discussed.
Published Version
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