PWB Z Interconnect Technology - Electrical Performance

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Driven mainly by Moore's law, there is an ever accelerating drive for smaller, lighter, higher function, and lower power electronics. For PWBs this translates into higher wiring and component densities with ever increasing electrical performance requirements. As high speed serial data rates reach 30 Gbps and beyond, design considerations to promote signal integrity become ever more important. These tighter signal integrity constraints put increased emphasis on via stub effects, via to trace crosstalk in BGA escapes, and adequate ground stitch vias around layer transition vias. With the maturation of sintered paste VIAs in PWBs, VIA structures can be assembled to span only the layers to be connected. This paste technology allows vias to be specifically tailored to only connect the required layers. VIA stubs and their adverse SI effects for high speed signaling are completely eliminated. The elimination of via stubs also makes PWB fabrication easier by removing the need to backdrill or counterbore high speed signal vias. This increases yields and reduces costs associated with this complex and tight tolerance process. In addition to manufacturing advantages provided by Z technology, increased wireability is enabled by opening up area above and below the layers being connected, as well as the ability to use smaller diameter VIAs. These smaller vias also help to reduce crosstalk between high speed wiring channels. Z Interconnect technology also reduces BGA escape crosstalk by the ability to route in areas where via stubs have been removed, and also allows for the tailoring of ground stitch vias to only connect the ground planes associated with the specific stripline environments. However, Z VIAs usually require more pads within the padstack than conventional VIAs (cannot strip pads from non-connection layers) and the resistivity of the paste can be as much as 30 times greater than copper. This paper will quantify the high frequency signal characteristics associated with a PWB design using i3 Electronics sintered paste Z-VIAs. Results are presented based on modeling which is correlated with test vehicle measurements. Modeling also addresses manufacturing tolerances. Suggestions are made for optimizing passive channel structures to use this technology in support of high speed serial interconnects. Integration of i3's 2s1p Cores into new compact high speed stripline structures, which can be built without expensive subassemblies and sequential lamination processes, is also presented. These cores implement the positive aspects of Z Interconnect technology to eliminate via stubs and increase wireability in dense areas. Comparisons of Z Interconnect technology are also made to alternate methods of PWB construction to explain the risks and benefits of this technology.